1. Technical Field
The present invention relates to a semiconductor device having a noise removal circuit for a control clock.
2. Background Art
Semiconductor devices (LSIs) for controlling predetermined electronic devices are widely in use. As shown in FIG. 5, such a controlling semiconductor device receives a control signal such as an external clock signal CL, a chip select signal CE, or the like from an external controlling computer, and communicates data through a data input line DI and a data output line DO. A controlling system for such a semiconductor device (LSI) is applied, for example, to an optical disk replaying LSI to be equipped on a vehicle or the like.
For example, in a communication data receiving circuit as shown in FIG. 6, the external clock signal CL is high while data A0˜A7 are time-sequentially input to the data input line DI as shown in a timing chart of FIG. 7, so that the data A0˜A7 are sequentially held in the stages of flip flops included in a shift circuit 10, and in this state, the chip select signal CE falls so that the data A0˜A7 are read to the flip flops included in a serial-to-parallel (SP) conversion circuit 12, converted from serial to parallel, and received. Similarly, the communication data transmitting circuit is controlled by the control signal such as the external clock signal CL and the chip select signal CE.
The controlling computer is directly connected to the controlling semiconductor device, and when noise is superposed on the control signal such as the external clock signal CL and the chip select signal CE, there is a possibility that an error will occur in the data communication.
Here, as shown in FIG. 8, a noise removal circuit which uses a high-speed internal clock signal ICL generated inside the controlling semiconductor device is incorporated in the controlling semiconductor device, to apply a process to remove the noise from the control signal or the like. The noise removal circuit comprises a shift circuit 14 in which a plurality of stages of flip flops are connected, a majority determining circuit 16, and an output holding circuit 18. The control signals such as the external clock signal CL and the chip select signal CE are input to the shift circuit 14 as input signals, and the shift circuit 14 holds the input signals while shifting the input signals according to the timing of rising of the internal clock signal ICL. Shift signals S1˜S4 which are output from the flip flops of later stages of the shift circuit 14 are input to the majority determining circuit 16. The majority determining circuit 16 finds the majority of either the high level or the low level signal among the shift signals S1˜S4, and outputs the signal level of the signal with a higher occurrence. When the numbers of the high level and the low level are equal to each other, a feedback signal FB from the output holding circuit 18 is output without any processing. The output holding circuit 18 holds and outputs an output signal from the majority determining circuit 16 in synchronization with the internal clock signal ICL.
With such a process, influence of noise superposed on the control signal such as the external clock signal CL and the chip select signal CE is reduced.
When the noise removal process is executed using the majority determining circuit 16, the internal clock signal ICL has a frequency which is approximately 20 times that of the control signal such as the external clock signal CL and the chip select signal CE. In the noise removal circuit of FIG. 8, because the output is determined through the majority process according to the result of latching the input signal with 4 stages of flip flops, the internal clock signal ICL must have a frequency of at least 4 times that of the input signal. For example, while the external clock signal CL has a frequency of approximately 2.5 MHz, the internal clock signal ICL has a frequency of approximately 60 MHz.
However, when the frequency of the internal clock signal ICL of the controlling semiconductor device is low, if the number of latch stages is high in the noise removal circuit, the output of the noise removal circuit cannot follow the change (frequency) of the control signal such as the external clock signal CL and the chip select signal CE. On the other hand, if the number of latch stages in the noise removal circuit is reduced, the number of input signals for the majority process is reduced, and the precision of noise removal is also reduced.